1. Field of the Invention
The invention relates to a method of fabricating semiconductor structures, and more particularly, to the formation of polysilicon plugs for DRAM memory cells.
2. Description of the Prior Art
As semiconductor memory devices continue to be scaled down, it is increasingly difficult to provide connectivity between devices while not sacrificing the improved packing density of the latest technology. Typically in the art, adjacent dynamic random access memory, or DRAM word lines are spaced very closely together. To construct a viable circuit, a connection must be made from the substrate active area between two adjacent word lines up to the metal interconnecting layers above the word lines. Unfortunately, the current technology is not capable of making such a contact opening at the small spacing of the word lines.
To overcome this problem, the approach of the prior art is to create a self-aligned contact, or SAC, structure. The key techniques in making the SAC are the use of material selective etches and protective films to advantageously cover the word lines from the selective etches. For instance, if a thick silicon oxide interlevel isolation must be etched to create the contact opening, then a thin layer of silicon nitride film might be used to cover the word line. In this case, a selective etch that attacks silicon oxide rapidly but silicon nitride very slowly could be used. Once the contact opening is etched, the silicon nitride protective layer would be carefully removed to complete the contact opening to the substrate. Once the contact opening is made, typically a polysilicon layer is deposited to fill the contact opening. Often, a polishing step is then used to etch down this polysilicon layer until only a plug of polysilicon remains to fill the contact opening. In this way a contact opening that is larger than the available word line space can be used in the connection from substrate to interconnect level.
A particular step in the formation of the SAC polysilicon plug for a DRAM in the prior art is shown in FIG. 1. A silicon substrate 11 is provided. Not shown in this illustration are the features below the surface of the substrate 11 such as shallow trench isolation structures and the source and drains of the active devices.
At the surface of the substrate 11, two DRAM word lines are shown. These word lines are constructed as a stack of gate silicon oxide 12, polysilicon gate 13, and capping silicon nitride 14. Sidewall spacers 15 of silicon nitride are also provided overlying the word lines and the substrate 11 surface adjacent the word lines is a layer of pad silicon oxide 16. A layer of interpoly oxide 17, or IPO, is shown after deposition.
In the typical prior art, at this point the wafer is subjected to a chemical mechanical polishing, or CMP, step to planarize the IPO layer 17. After CMP, a photoresist layer 18 is deposited and patterned using photolithography as shown in FIG. 2. The photoresist pattern opening determines the location of the SAC hole. Note how this opening is substantially wider than the potential substrate 11 contact width between the sidewall spacers 15 of the two word lines.
After the photoresist 18 is patterned, the SAC hole is etched. As shown in FIG. 3, a thin, high temperature film, or HTF, of doped polysilicon 19 is deposited overlying the entire exposed surface. Next, a thick layer of doped polysilicon 20 is deposited overlying the HTF polysilicon 19. The polysilicon surface layer 20 is now subjected to a CMP process. As shown in FIG. 4, the polysilicon layers 19 and 20 are polished down to the surface of the IPO layer 17. This completes the formation of the polysilicon plug in the SAC hole.
Notice that this prior art sequence requires two different CMP steps to complete. Further, in the art it is common to have different CMP slurry compositions for polysilicon and silicon oxide. Further yet, by subjecting the IPO layer to CMP before the SAC etch step, additional wafer to wafer variation is introduced in the thickness of IPO that must be etched in the SAC etch step.
Several prior art approaches deal with CMP processes to planarize the IPO layer. U.S. Pat. No. 5,792,684 to Lee et al shows an IPO planarization process. U.S. Pat. No. 5,747,382 to Huang et al discloses a two-step planarization process using CMP and reactive ion etching. U.S. Pat. No. 5,723,381 to Grewal et al teaches a SAC and IPO CMP process. U.S. Pat. No. 5,229,326 to Dennison shows a planarization process.